22-Elec-B5 Advanced Electronics
Worked solutions to 14 past sittings (2013–2019), 71 questions. Pick a sitting, or start from a topic below.
- December 2019
- December 2018
- May 2018
- December 2017
- May 2017
- December 2016
- May 2016
- December 2015
- May 2015
- December 2014
- May 2014
- December 2013
- May 2013
- Undated paper
Topics across the sittings
Topics that come up in more than one sitting, taken from the headings of our worked solutions. A topic counts once per sitting.
- Input (7 sittings): December 2019 Q5 · December 2018 Q4 · May 2016 Q5 · December 2015 Q4 · December 2014 Q5 · May 2014 Q2 · May 2013 Q2
- Output Resistance (7 sittings): December 2019 Q5 · December 2017 Q1 · May 2016 Q5 · December 2015 Q4 · December 2014 Q5 · May 2014 Q2 · May 2013 Q2
- Bandwidth (5 sittings): May 2018 Q4 · May 2016 Q4 · December 2015 Q3 · December 2014 Q2 · May 2013 Q1
- Centre Frequency (5 sittings): May 2018 Q4 · May 2016 Q4 · December 2015 Q3 · December 2014 Q2 · May 2014 Q3
- Common-Source Amplifier (5 sittings): December 2019 Q2 · December 2017 Q4 · May 2016 Q2 · December 2015 Q5 · December 2014 Q3
- Efficiency (5 sittings): December 2019 Q3 · May 2016 Q1 · December 2015 Q1 · May 2014 Q5 · December 2013 Q3
- Gain (5 sittings): May 2018 Q4 · December 2016 Q1 · December 2015 Q3 · December 2014 Q2 · May 2013 Q1
- Common-Emitter Amplifier (4 sittings): May 2018 Q3 · December 2017 Q3 · December 2015 Q2 · Undated paper Q5
- Mid-Band Gain (4 sittings): December 2019 Q2 · December 2015 Q2 · May 2015 Q2 · May 2014 Q3
- Device Dissipation (3 sittings): December 2019 Q3 · May 2016 Q1 · May 2014 Q5
- Device Sizing (3 sittings): May 2018 Q1 · May 2017 Q1 · Undated paper Q3
- Differential Gain (3 sittings): May 2018 Q1 · May 2017 Q1 · Undated paper Q3
- Feedback Factor (3 sittings): May 2018 Q2 · December 2017 Q5 · May 2017 Q2
- Loop Gain (3 sittings): May 2018 Q2 · December 2017 Q5 · May 2017 Q2
- Series Voltage Regulator (3 sittings): December 2015 Q1 · December 2014 Q1 · December 2013 Q3
Questions by sitting
December 2019
- Question 1: MOS Differential Amplifier — Bias, Transconductance, Full Current Switching and Input Offset
- Question 2: Common-Source Amplifier — Mid-Band Gain and Design of the Coupling and Bypass Capacitors
- Question 3: Class B Output Stage — Output Power, Device Dissipation and Efficiency
- Question 4: Op-Amp with a Diode-Connected Transistor in the Feedback Path — A Logarithmic Amplifier
- Question 5: Common-Gate Amplifier inside a Voltage-Series Feedback Loop — Input and Output Resistance
December 2018
- Question 1: Design of a CMOS Differential Amplifier
- Question 2: Class-B Push-Pull Output Stage
- Question 3: Miller Compensation of a Two-Pole Op Amp
- Question 4: Input and Output Resistance of a Feedback Amplifier
- Question 5: Tuned Amplifier with a Gate Tank
May 2018
- Question 1: 0.18 µm CMOS Differential Pair — Device Sizing and Differential Gain
- Question 2: Series–Shunt Feedback Amplifier — Feedback Factor, Design Ratio and Loop Gain
- Question 3: Common-Emitter Amplifier — Sizing $C_{C1}$, $C_{C2}$ and $C_E$ for a 100 Hz Lower Corner
- Question 4: Tuned Amplifier with a Gate Tank — Centre Frequency, Gain and Bandwidth
- Question 5: Bipolar Cascode Amplifier — Voltage Gain
December 2017
- Question 1: Bipolar Cascode Current Source — Output Resistance and Output Compliance
- Question 2: Op-Amp with a Grounded-Gate MOSFET in the Feedback Path — Transfer Law and Function
- Question 3: Common-Emitter Amplifier — Sizing the Three Capacitors for a 100 Hz Lower Corner
- Question 4: Common-Source Amplifier — Mid-Band Gain With and Without the Source Bypass, and the New $f_H$
- Question 5: Two-Stage Series–Shunt Feedback Amplifier — Feedback Factor, Loop Gain and Closed-Loop Gain
May 2017
- Question 1: Single-Stage CMOS Differential Amplifier — Device Sizing and Differential Gain
- Question 2: Series–Shunt Feedback Amplifier — Feedback Factor, Loop Gain and Closed-Loop Gain
- Question 3: Lower Cutoff Frequency of a Common-Emitter Amplifier — Coupling and Bypass Capacitor Design
- Question 4: RC Oscillator — Frequency of Oscillation, Start-Up Condition and Amplitude Stabilisation
- Question 5: Bipolar Cascode — Voltage Gain
December 2016
- Question 1: DC Bias, Gain and Terminal Resistances of a PNP–NPN Two-Stage Amplifier
- Question 2: Bias Design and Small-Signal Performance of an NMOS Cascode
- Question 3: Shunt–Shunt Feedback Trans-Resistance Amplifier
- Question 4: Standby Power, Swing, Drive, Output Power and Efficiency of a Class AB Stage
- Question 5: Miller (Pole-Splitting) Compensation of a Two-Pole Op Amp
May 2016
- Question 1: Class-B push–pull output stage — load power, device dissipation and efficiency
- Question 2: Common-source amplifier — mid-band gain with and without the source bypass, and the resulting bandwidth
- Question 3: Bipolar cascode (Razavi Example 9.9) — mid-band voltage gain
- Question 4: Tuned amplifier with a gate tank — centre frequency, resonant gain and bandwidth
- Question 5: Shunt feedback around a common-source stage — input and output resistance
December 2015
- Question 1: Series voltage regulator — output voltage, line ripple and efficiency
- Question 2: Common-emitter amplifier — mid-band gain and the two 3 dB frequencies
- Question 3: Tuned amplifier with a gate tank — centre frequency, gain and bandwidth
- Question 4: Shunt–shunt feedback amplifier — input and output resistance
- Question 5: Common-source amplifier — bypassed and unbypassed source, and the new 3 dB frequency
May 2015
- Question 1: Bipolar Cascode with an Ideal Current-Source Load
- Question 2: Common-Emitter Stage — Mid-Band Gain and Both 3 dB Frequencies
- Question 3: Complementary MOS Class B Output Stage
- Question 4: MOS Differential Pair with Current-Source Loads
- Question 5: Sizing the Output Coupling Capacitor of an Audio CS Stage
December 2014
- Question 1: Series Voltage Regulator
- Question 2: Tuned Amplifier — Centre Frequency, Gain and Bandwidth
- Question 3: Common-Source Amplifier — Gain and High-Frequency Response
- Question 4: Bipolar Cascode Voltage Gain
- Question 5: Feedback Amplifier — Input and Output Resistance
May 2014
- Question 1: MOSFET Differential Pair — Design, Common-Mode Behaviour and Loaded Waveforms
- Question 2: Common-Gate Stage with Series-Shunt Feedback — Input and Output Resistance
- Question 3: Tuned Amplifier — Centre Frequency, Mid-Band Gain and 3 dB Bandwidth
- Question 4: BJT Cascode Amplifier — Voltage Gain
- Question 5: Class-B Push-Pull Output Stage — Power, Device Dissipation and Efficiency
December 2013
- Question 1: MOSFET Differential Pair with Current‑Source Loads
- Question 2: PNP Common‑Emitter Stage — Mid‑band Gain and Both 3 dB Corners
- Question 3: Series Voltage Regulator — Output, Ripple and Efficiency
- Question 4: Zener‑Limited Astable Function Generator — Output Waveform
- Question 5: Common‑Source Amplifier — Effect of Removing the Source Bypass Capacitor
May 2013
- Question 1: PNP common-emitter amplifier — gain and bandwidth
- Question 2: Feedback amplifier — input and output resistance
- Question 3: Cascode differential pair — gain, input range and CMRR
- Question 4: Eight-bit analog-to-digital conversion — resolution and quantisation error
- Question 5: Tuned amplifier with a series-resonant trap
- Question 6: Class-AB output stage inside error amplifiers
Undated paper
- Question 1: 8-bit Analog-to-Digital Conversion — Resolution, Codes and Quantisation Error
- Question 2: Class-AB Output Stage Enclosed by Two Error Amplifiers
- Question 3: 0.18 µm CMOS Differential Pair — Device Sizing and Differential Gain
- Question 4: CMOS Current-Source Bias Generator — Sizing, Ratioing and Compliance
- Question 5: Common-Emitter Amplifier — Sizing the Coupling and Bypass Capacitors for a 100 Hz Corner