NivaarExam Prep

22-Elec-A4 Digital Systems and Computers

Worked solutions to 14 past sittings (2013–2019), 84 questions. Pick a sitting, or start from a topic below.

Topics across the sittings

Topics that come up in more than one sitting, taken from the headings of our worked solutions. A topic counts once per sitting.

Questions by sitting

December 2019

  1. Question 1: Boolean minimization and hazards
  2. Question 2: Function realization — gates, MUX, decoder
  3. Question 3: Analysis of a two-RS-flip-flop circuit
  4. Question 4: HC11 address-decoded I/O routing
  5. Question 5: Serial character echo with case swap; TxD waveforms
  6. Question 6: Parallel I/O — CPU methods and device handshaking

December 2018

  1. Question 1: NAND / NOR gate realizations of a Boolean function
  2. Question 2: Synchronous counter with JK flip-flops
  3. Question 3: K-map minimization and PAL/PLA choice
  4. Question 4: Computer-system components and CPU registers
  5. Question 5: Big-endian storage and the stack
  6. Question 6: Two-digit seven-segment display driver

May 2018

  1. Question 1: Combinational circuit — even / equal-MSB detector and odd-sum detector
  2. Question 2: Start/stop 3-bit synchronous counter
  3. Question 3: RS + T flip-flop state machine
  4. Question 4: Shift registers in serial communication
  5. Question 5: Parallel I/O — CPU communication and handshake protocols
  6. Question 6: Multiplexed seven-segment display driver (68HC11)

December 2017

  1. Question 1: Boolean minimisation and hazards
  2. Question 2: Prime implicants and minimal SoP
  3. Question 3: Multilevel function and NOR-only synthesis
  4. Question 4: Two-bit subtractor and HS/FS cascade
  5. Question 5: RS flip-flop finite-state machine
  6. Question 6: Timer interfaces and the interrupt process

May 2017

  1. Question 1: Boolean minimisation, K-map verification and hazard removal
  2. Question 2: Synchronous counter design with D flip-flops
  3. Question 3: 2-bit adder outputs by K-map, implemented in a PAL
  4. Question 4: FSM built from an 8:1 MUX, a T and a D flip-flop
  5. Question 5: Parallel I/O — CPU polling vs interrupts, and handshake protocols
  6. Question 6: 68HC11 parallel-port address decoding, read strobes and handshake timing

December 2016

  1. Question 1: PoS to truth table, canonical SoP, minimal SoP and hazard removal
  2. Question 2: Two RS flip-flops: logic equations, state table and state diagram
  3. Question 3: 3-input / 4-output logic: K-map minimization and PAL vs PLA
  4. Question 4: NOR universality, combinational vs sequential, synchronous vs asynchronous counters
  5. Question 5: Memory-mapped chip-select decoding
  6. Question 6: Two-digit seven-segment display drive and current-limit resistor

May 2016

  1. Question 1: Map simplification, prime implicants and hazards
  2. Question 2: Analysis of a two JK flip-flop sequential circuit
  3. Question 3: Asynchronous binary and decade counters using T flip-flops
  4. Question 4: A static memory cell built from cascaded inverters and tri-state buffers
  5. Question 5: Computer system components, microcontrollers and CPU registers
  6. Question 6: Driving six multiplexed seven-segment displays

December 2015

  1. Question 1: Truth table, canonical and minimal POS, NOR-only synthesis
  2. Question 2: 3-bit synchronous counter with a count-enable input
  3. Question 3: MUX-based finite state machine with T and D flip-flops
  4. Question 4: Address decoding and I/O routing on an HC11 system
  5. Question 5: Building a 64 Kbyte memory from 16K × 4 chips
  6. Question 6: Fundamentals: gates, circuit classes, state machines and counters

May 2015

  1. Question 1: Gate-level realisations of a Boolean function
  2. Question 2: Flip-flop conversion by excitation table and K-map
  3. Question 3: Two-bit subtractor
  4. Question 4: Analysis of a two-flip-flop sequential circuit
  5. Question 5: Interrupt-driven serial echo and RS-232 waveforms
  6. Question 6: Big-endian storage and stack operation

December 2014

  1. Question 1: Boolean synthesis, minimisation and hazard analysis
  2. Question 2: Multiplexer and decoder realisations
  3. Question 3: Four-output minimisation and PLA implementation
  4. Question 4: RS flip-flop finite state machine
  5. Question 5: HC11 address decoding and I/O routing
  6. Question 6: Parallel I/O — CPU polling versus interrupts, and handshake protocols

May 2014

  1. Question 1: Truth Table, Canonical Form, Minimisation and Static Hazards
  2. Question 2: Synchronous Counter Design with JK Flip-Flops
  3. Question 3: Analysis of a Combinational MSI Circuit
  4. Question 4: Shift Registers in a Serial Communication Port
  5. Question 5: Multiplexed Two-Digit Seven-Segment Display
  6. Question 6: Computer System Organisation and the CPU Register Set

December 2013

  1. Question 1: K-map Minimisation and Static Hazards
  2. Question 2: Multiplexer and Decoder Implementations
  3. Question 3: Four-Output Combinational Circuit and PLD Choice
  4. Question 4: Synchronous Up/Down Counter with T Flip-Flops
  5. Question 5: Serial Communication Protocols and Framing
  6. Question 6: Memory System Sizing and Bus Widths

May 2013

  1. Question 1: Combinational Design from a Word Statement
  2. Question 2: Asynchronous Binary and Decade Counters
  3. Question 3: JK Finite State Machine — 2-Bit Up/Down Counter
  4. Question 4: Shift Registers in a Serial Communication Port
  5. Question 5: Big-Endian Storage and the Stack
  6. Question 6: Buses, Memory Space and Address Decoding

Undated paper

  1. Question 1: K-map minimisation and hazards (12 pts)
  2. Question 2: Synchronous up/down counter with JK flip-flops (12 pts)
  3. Question 3: Multi-output logic and PLA implementation (12 pts)
  4. Question 4: Analysis of an RS + T flip-flop circuit (12 pts)
  5. Question 5: HC11 memory-mapped I/O routing (12 pts)
  6. Question 6: 64 KB memory from 16K×4 modules (12 pts)