25-Comp-A3 Computer Architecture
Worked solutions to 8 past sittings (2013–2018), 48 questions. Pick a sitting, or start from a topic below.
Topics across the sittings
Topics that come up in more than one sitting, taken from the headings of our worked solutions. A topic counts once per sitting.
- Cache Organization (3 sittings): May 2016 Q1 · May 2014 Q3 · May 2013 Q3
- Addressing Modes (2 sittings): May 2016 Q6 · December 2015 Q6
- Composition (2 sittings): May 2014 Q6 · May 2013 Q6
- Control-Unit Styles (2 sittings): May 2016 Q5 · December 2015 Q1
- IEEE-754 Decoding (2 sittings): May 2016 Q4 · December 2015 Q4
- Instruction Encoding (2 sittings): December 2015 Q3 · May 2013 Q1
- Memory Chip Capacity (2 sittings): May 2014 Q6 · May 2013 Q6
Questions by sitting
December 2018
December 2017
May 2017
- Question 1: Two's-Complement Addition, IEEE-754 Multiply Precision, and Byte-Addressable Array Layout
- Question 2: Opcode Space and Register-Field Width in a Fixed 32-bit Instruction Encoding
- Question 3: Minimum Memory Traffic for Program Execution, and Polling vs. Interrupt-Driven I/O
- Question 4: Set-Associative Cache Indexing, Address Decoding, and Registers vs. Caches
- Question 5: Memory-Chip Capacity, Composing a Wider/Deeper Memory, and Byte-Interleaved Chip Selection
- Question 6: Multi-Cycle CPI Trade-off Between Clock Speed and Instruction Cost, and the Rise of Caches in the x86 Family
December 2016
May 2016
- Question 1: Cache Organization, Control-Unit Signals, and Bus-Width Transfer Rate
- Question 2: Cache Block Size, I/O Drawbacks, and Parallelism
- Question 3: Cache Write Policy, Instruction Encoding Length, and Binary Division Hardware
- Question 4: Memory Volatility, IEEE-754 Decoding, and Variable-Length Encoding Savings
- Question 5: Memory-Hierarchy Access Time, RPN-to-Infix, and Control-Unit Styles
- Question 6: Branch Prediction, Addressing Modes, Shift Types, and Non-Volatile Memory Families
December 2015
- Question 1: Cache Size, Control-Unit Style, and Bus-Width Performance
- Question 2: Cache Replacement, I/O Techniques, and RISC Design
- Question 3: Cache Write Consistency, Instruction Encoding, and Multiplication Hardware
- Question 4: DRAM vs. SRAM, IEEE-754 Decoding, and Instruction-Encoding Sizing
- Question 5: Hit-Rate Sizing, Infix-to-RPN, and Control-Unit Design
- Question 6: Unified Memory, Addressing Modes, and Micro-Operation Sequences
May 2014
- Question 1: Instruction Set Extension, Memory Traffic, and I/O
- Question 2: Signed/Unsigned Arithmetic, Floating-Point Precision, and Array Addressing
- Question 3: Cache Organization and the Register/Cache Tradeoff
- Question 4: Pipelining, Parallel Execution Strategies, and Hardware Specialization
- Question 5: Multi-Cycle CPU Performance Comparison
- Question 6: Memory Chip Capacity, Composition, and Byte-Interleaved Bus Interfacing
May 2013
- Question 1: Instruction Encoding and Memory Addressing
- Question 2: Addressing Arrays and Linked Lists
- Question 3: Cache Organization and Performance
- Question 4: Calling Conventions and Unsigned Arithmetic
- Question 5: Multicycle CPU Performance Comparison
- Question 6: Memory Chip Capacity, Composition, and Bus Interfacing