25-Comp-A2 Digital Systems Design
Worked solutions to 7 past sittings (2014–2019), 42 questions. Pick a sitting, or start from a topic below.
Topics across the sittings
Topics that come up in more than one sitting, taken from the headings of our worked solutions. A topic counts once per sitting.
- 64Kbyte Memory Address Decoding (7 sittings): December 2019 Q5 · December 2018 Q5 · May 2018 Q5 · December 2016 Q5 · May 2016 Q5 · December 2014 Q5 · Undated paper Q5
- Digital Design (7 sittings): December 2019 Q1 · December 2018 Q1 · May 2018 Q1 · December 2016 Q1 · May 2016 Q1 · December 2014 Q1 · Undated paper Q1
- VHDL Concepts (7 sittings): December 2019 Q1 · December 2018 Q1 · May 2018 Q1 · December 2016 Q1 · May 2016 Q1 · December 2014 Q1 · Undated paper Q1
- 3-Bit Synchronous Counter with Count-Enable (5 sittings): December 2019 Q4 · May 2018 Q4 · December 2016 Q4 · December 2014 Q4 · Undated paper Q4
- Interrupt Processing (5 sittings): December 2019 Q6 · December 2018 Q6 · May 2018 Q6 · December 2016 Q6 · Undated paper Q6
- 4-Bit Synchronous Counter with Count-Enable (2 sittings): December 2018 Q4 · May 2016 Q4
- Interrupt-Driven I/O (2 sittings): May 2016 Q6 · December 2014 Q6
- Variable-Entered Maps (2 sittings): December 2018 Q3 · May 2016 Q3
Questions by sitting
December 2019
- Question 1: Digital Design and VHDL Concepts
- Question 2: Function Realization with an 8-to-1 Multiplexer
- Question 3: Boolean-Algebra Minimization from a Product-of-Sums Expression
- Question 4: 3-Bit Synchronous Counter with Count-Enable
- Question 5: 64Kbyte Memory Address Decoding
- Question 6: Interrupt Processing
December 2018
- Question 1: Digital Design and VHDL Concepts
- Question 2: PAL Implementation of Two Functions
- Question 3: Variable-Entered Map and Karnaugh Map Minimization
- Question 4: 4-Bit Synchronous Counter with Count-Enable
- Question 5: 64Kbyte Memory Address Decoding
- Question 6: Interrupt Processing
May 2018
- Question 1: Digital Design and VHDL Concepts
- Question 2: Function Realization with an 8-to-1 Multiplexer
- Question 3: Boolean-Algebra Minimization from a Product-of-Sums Expression
- Question 4: 3-Bit Synchronous Counter with Count-Enable
- Question 5: 64Kbyte Memory Address Decoding
- Question 6: Interrupt Processing
December 2016
- Question 1: Digital Design and VHDL Concepts
- Question 2: Function Realization with an 8-to-1 Multiplexer
- Question 3: Boolean-Algebra Minimization from a Product-of-Sums Expression
- Question 4: 3-Bit Synchronous Counter with Count-Enable
- Question 5: 64Kbyte Memory Address Decoding
- Question 6: Interrupt Processing
May 2016
- Question 1: Digital Design and VHDL Concepts
- Question 2: PAL Implementation of Two Sum-of-Products Functions
- Question 3: Variable-Entered Maps
- Question 4: 4-Bit Synchronous Counter with Count-Enable
- Question 5: 64Kbyte Memory Address Decoding
- Question 6: Interrupt-Driven I/O
December 2014
- Question 1: Digital Design and VHDL Concepts
- Question 2: Function Realization with an 8-to-1 Multiplexer
- Question 3: Canonical and Minimized Forms from a POS Expression
- Question 4: 3-Bit Synchronous Counter with Count-Enable
- Question 5: 64Kbyte Memory Address Decoding
- Question 6: Interrupt-Driven I/O
Undated paper
- Question 1: Digital Design and VHDL Concepts
- Question 2: Function Realization with an 8-to-1 Multiplexer
- Question 3: Boolean-Algebra Minimization from a Product-of-Sums Expression
- Question 4: 3-Bit Synchronous Counter with Count-Enable
- Question 5: 64Kbyte Memory Address Decoding
- Question 6: Interrupt Processing