17-Comp-A1
Worked solutions to 3 past sittings (2018–2019), 21 questions. Pick a sitting, or start from a topic below.
Topics across the sittings
Topics that come up in more than one sitting, taken from the headings of our worked solutions. A topic counts once per sitting.
- Sizing (2 sittings): December 2019 Q6 · Undated paper Q6
Questions by sitting
December 2019
- Question 1: Two-Stage Diode Limiter with Resistive Divider
- Question 2: MOS Cascade — Diode-Loaded CS Stage Buffered by a Source Follower
- Question 3: Matched Difference Amplifier — Gain and Clipping Limit
- Question 4: Split-Supply Common-Emitter Amplifier
- Question 5: Three-Stage RC Phase-Shift Oscillator
- Question 6: Symmetric CMOS Inverter — Sizing, VTC and Speed
- Question 7: 4-Bit Binary-Weighted Current-Mirror DAC
December 2018
- Question 1: Two-Sided Diode Voltage Limiter
- Question 2: MOS Amplifier with Current-Mirror Active Load
- Question 3: Active Bandpass Amplifier with Bias-Current Compensation
- Question 4: BJT Emitter-Follower with Current-Source Bias
- Question 5: Astable (Free-Running) Multivibrator
- Question 6: CMOS Complex-Gate Transistor Sizing
- Question 7: Integrator-Comparator Voltage-to-Time Converter
Undated paper
- Question 1: Current-Source-Driven Full-Wave Bridge Rectifier
- Question 2: Fixed-Bias BJT Amplifier — Design and the $R_b=0$ Failure Case
- Question 3: Inverting Op-Amp with Zener-Diode Output Limiter
- Question 4: Common-Source MOSFET Amplifier — Max-Swing Design
- Question 5: DC Restorer (Clamper) Driving a Voltage Follower — Steady State at $v_{in}=0$
- Question 6: CMOS AND-OR-INVERT (AOI21) Gate — Sizing and Propagation Delay
- Question 7: 6-Bit R-2R Ladder DAC