NivaarExam Prep

04-BS-8

Worked solutions to 12 past sittings (2013–2019), 60 questions. Pick a sitting, or start from a topic below.

Topics across the sittings

Topics that come up in more than one sitting, taken from the headings of our worked solutions. A topic counts once per sitting.

Questions by sitting

December 2019

  1. Question 1: Synchronous Up-Down Counter (Non-Binary Sequences)
  2. Question 2: Boolean Minimization — POS/NOR, SOP/AND-OR, and NAND-Only Realizations
  3. Question 3: D-from-JK, Combinations, a Boolean Evaluation, and a Shift-Register/JK Synthesis
  4. Question 4: Excess-3 Code, a 3-Bit NAND-Only Converter, and a PAL16L8 Implementation
  5. Question 5: Even-Parity Generator for a Synchronized 5-Bit Serial Stream

December 2018

  1. Question 1: Synchronous Up/Down Mod-8 Counter
  2. Question 2: Flip-Flop Conversion, Machine Types, Number Representations
  3. Question 3: 4-Bit Negative-Magnitude → 2’s-Complement Converter
  4. Question 4: Serial Sequence Detector (“1110”) on a PAL16R4
  5. Question 5: 4-Bit Hex → Braille Converter

May 2018

  1. Question 1: Boolean Expression Evaluation and a Dual Crossbar-Switch Network
  2. Question 2: FPGA Architecture, and a 2’s-Complement→Sign-Magnitude Converter
  3. Question 3: Sequence-Detector FSM — “1100” After ≥3 Zeros
  4. Question 4: T Flip-Flop from a JK, and a 2-Bit Shift-Register State Detector
  5. Question 5: Barrel Shifter — Concept and a 4:1-MUX Realization

December 2017

  1. Question 1: Synchronous Counter with a Non-Binary Repeating Sequence
  2. Question 2: Combinational Divide-by-4 Circuit
  3. Question 3: Number Representation, Flip-Flop Identification & Boolean Minimization
  4. Question 4: Weighted-Share Voting Logic Circuit
  5. Question 5: Flip-Flop Conversion, Frequency Division and Serial 2’s-Complement

May 2017

  1. Question 1: FPGA/PLD Architecture & Sign-Magnitude to 2’s-Complement Converter
  2. Question 2: Sequence Detector with Lockout Condition (0101, disabled by 1100)
  3. Question 3: Flip-Flop Conversion, Boolean Evaluation, Characteristic Table, 4-1 MUX
  4. Question 4: Two-Flip-Flop Counter — Synchronicity, State Detection, Timing
  5. Question 5: Boolean Function Minimization — POS, SOP, and NAND-Only Realizations

December 2016

  1. Question 1: Serial-Delay Circuit Design — Shift Register Implementation
  2. Question 2: Adders, BCD, and NAND-Gate Minimization
  3. Question 3: Memory Control Logic — Decoder and PAL Realizations
  4. Question 4: Finite State Machine Design with D Flip-Flops
  5. Question 5: Flip-Flop Conversion, Frequency Division, and Shift-Register Analysis

May 2016

  1. Question 1: Combinational Logic — PLD Survey, K-map/NAND Synthesis, Decoder Realization
  2. Question 2: Synchronous Sequence Detector — 0110-with-1000-Lockout
  3. Question 3: Short-Answer Set — Flip-Flop Conversion, Boolean Evaluation, Characteristic Tables, Memory Sizing, Gate Network
  4. Question 4: Traffic-Light Sequence Controller
  5. Question 5: Number Representation, Adder Architectures, Ripple-Carry Design

December 2015

  1. Question 1: 220-Space Parking Garage Counter
  2. Question 2: 3-Bit Gray Code and Gray-to-BCD Conversion
  3. Question 3: BCD-to-Braille Converter
  4. Question 4: EVEN/ODD Parity-Tracking FSM
  5. Question 5: Flip-Flop Conversion, Frequency Divider, Shift-Register Simulation

May 2015

  1. Question 1: Serial Sequence Detector (11010) with JK Flip-Flops
  2. Question 2: ROM vs. FPGA, PAL16L8 and Decoder Implementation
  3. Question 3: Short-Answer Justify Questions
  4. Question 4: D Flip-Flop from SR Flip-Flop; Minimum-Hardware Down-Counter
  5. Question 5: Combinational Multiplier (3-bit × Constant 3)

December 2014

  1. Question 1: Code Comparison, Gray-to-Binary Conversion and NAND Synthesis
  2. Question 2: PAL vs. FPGA, PAL16L8 Implementation and FPGA Logic Blocks
  3. Question 3: Finite State Machine Design with D Flip-Flops
  4. Question 4: D-from-JK Conversion and a Minimum-Flip-Flop Down Counter
  5. Question 5: 7-Bit Parity Generator and Checker Modification

May 2013

  1. Question 1: Gate-Level Circuit Analysis, NAND Synthesis and PLD Implementation
  2. Question 2: Multi-Output Karnaugh-Map Minimization with Shared Logic
  3. Question 3: Two's-Complement Representation and an 8-Bit Subtractor
  4. Question 4: JK-from-D Flip-Flop Conversion and a 4-Bit Barrel Shifter
  5. Question 5: Serial Parity Generator and Checker

Undated paper

  1. Question 1: Combination-Lock Sequence Detector
  2. Question 2: Traffic Light Controller
  3. Question 3: Synchronous Even-Number Counter
  4. Question 4: Boolean Simplification and K-map Minimization
  5. Question 5: JK Flip-Flop Synthesis and 2's-Complement Circuit